Digital communication chips or devices, such as those that receive data from an input/output (I/O) interface such as a peripheral components interconnect (PCI), a peripheral components interconnect extended (PCI-X), a peripheral components interconnect express (PCI-E) to the northbridge chipset, and/or that communicate across an asynchronous communication link may have clock speeds that are different from one another as a result of design factors, manufacturing factors, external factors such as temperature, and/or clock crystals having different frequencies. Thus, during communication, such a chip may receive data at a frequency different than the clock frequency at which the chip is operating. Thus, such communication chips often have a data buffer, such as an elastic buffer, for buffering receive data to compensate for such variations in receive data frequency within a specification range. In addition, data transmitted to such communication chips often includes transmit marker type data packets that also help the chip to compensate for such variations in receive data frequency within a specification range.
For example, such a chip may use an elastic data buffer to receive data so that consumption of the data by the chip is independent of the rate the data is received by the buffer until the buffer is empty or overflows. In addition the inclusion of marker type data packets in the receive data allows the chip to consume but ignore the marker data, or to drop or dispose of the marker data prior to consumption depending on whether the chip is receiving data faster or slower than the data is being consumed. As a result a chip that is consuming data faster than it is being received may consume and ignore marker data until its elastic buffer is empty and then simply wait for more data (e.g., provided that more data is received is within a specific time period that does not cause an error for the chip). Alternatively, such a chip that is consuming data more slowly than the data is being received can drop marker data and allow its elastic buffer to fill with received data (e.g., provided the data being received is within a specific frequency range that does not overflow the buffer).
As a result, chips or devices that support digital communication, such as chips that support communication via PCI, PCI-X, PCI-E, and/or other asynchronous communication or protocol may be designed to allow for differences in clock speeds or data received frequency within a parameter range.
Moreover, these chips or devices may be tested to ensure that their receiving circuitry and/or data buffer for receiving data comply with requirements, such as an allowable range of data receive clock speeds or frequencies over a time period as required by a protocol, communication, device, or chip specification.